Conventional automated test equipment (ATE) for IC testing is designed to exercise the device functionally. This functional testing involves providing the stimulus information that the IC device under test (DUT) is expected to receive in the target application (e.g., the target printed circuit board environment in which the device is intended to operate), and verifying that the DUT responds with the same outputs that were simulated in the design process. In effect, functional testing checks that the device meets its performance specifications. By definition, developing a functional test requires knowledge of how the device is supposed to function. Running a functional test requires an extremely capable and flexible test system. The system must quickly and precisely measure that each of a wide range of responses is within acceptable tolerances, and emulate various electrical environments in which the chip is supposed to function.
In addition, conventional ATE systems are capable of performing many other types of tests. Typically, each pin of the tester can be switched to a DC Parametric Measurement unit to perform DC parametric testing on the pins of the DUT. DC parametric testing is used to verify connectivity between the tester and the IC DUT, and to verify that there are no defects that cause the device's current and voltage characteristics to be outside of its specified range. Often, an ATE tester will provide per-pin DC parametric measurement capabilities for this purpose.
Also, the conventional ATE tester can push timing to its limits, allowing devices to be sorted into faster versus slower categories or bins. The ATE system may have analog instrumentation to test analog functions.
In order to perform functional testing, conventional ATE systems typically consist of several interconnected PC boards containing the logic necessary to drive signals to the device under test (DUT) and receive signals from the DUT. The circuitry also contains the ability to analyze the results of the data returned from the DUT. To accomplish the necessary tests and analysis, these systems may be organized such that much of the circuitry is designed for specialty tasks such as:                Providing some level of control of all of the other boards in the tester        Providing the ability to sequence the test vectors        Providing for multiple types and frequencies of clocking for the DUT and, in some cases, the tester        Providing for the storage of digital vectors (signals), and for their output to or input from the DUT, for their retention (in memory) and for their analysis. This includes the ability to compare the results for pass/fail and to perform certain other comparisons and mathematical analyses.        Providing high-precision signal formatting for the data to be driven to the device under test.        
Current systems contain a complex array of PC boards with this circuitry, arranged in a frame with backplanes and connectors designed to route the signals to and from the DUT. Because of this organization, signals must be propagated over relatively long distances from their origin to the DUT. In addition, the analysis of the data received from a single DUT pin must often be routed to controllers or computers in the system for a cumulative analysis. Transmitting this data over any significant distance takes more time. Often this time is significant when compared to the vector rate of the DUT. This can result in problems such as:                Delays in Determining Conditional Jumps: situations may arise in which the results of data from the DUT determine which of several possible vector sequences are to be next in control of the DUT.        Delays in Controlling Selective Data Capture: often some of the output from the DUT must be “captured” in the memory of the tester, but only if certain combinations of the DUT signals indicate it is ready to output this data        
In a traditional tester architecture, the length of time it takes for the tester to route the signals necessary to make these determinations often exceeds the time available in a vector period. This results in the necessity for introducing “dead cycles” into the DUT data stream. These dead cycles are intended to “freeze” the state of the DUT for a period of time while the signals are being routed and the necessary analysis performed. Unfortunately, introducing these dead cycles into a test data stream can result in causing the system to miss defects, or it may cause the DUT to lose synchronization with the tester. Therefore, a tester architecture that causes fewer situations of this sort will help to eliminate these problems and result in a higher quality test of the DUT.
Additionally, much of the architecture of the test equipment being employed today is designed to support precision edge placement and the formatting of multiple signal transitions (edges) in a single vector cycle. This capability is often necessary in certain types of testing. In these cases, the generation of complex waveforms with precise timing relationships to each other is necessary in the testing of the device. These signals allow the device to be tested using what are known as “functional” vectors. These vectors when applied using the precision timing and high-speed capability of the tester can be used to verify that the device being tested meets its timing specifications.